1. Field of the Invention
This invention relates to integrated circuits, and particularly to metal oxide semiconductor large scale integrated circuit (MOS LSI) devices having n-channel or p-channel MOS field effect transistors, such as are commonly used in hand calculators, home and office computers, automotive and industrial control systems and other commercial products. MOS LSI devices use numerous circuit designs to achieve specific functions. One of the circuit designs used in MOS LSI devices is a linear voltage regulator circuit, i.e., a circuit which provides a predetermined fixed output voltage to a variable load, which is relatively insensitive to variations in load current, changes in line or input voltage and variations in temperature. The invention circuit provides these features and is particularly suitable for manufacture by standard integrated circuit processing steps.
2. Description of the Prior Art
While many circuits exist that are useful as voltage reference sources, all such known circuits have a large number of components to effect a precise output voltage. Typical of one such circuit is the one disclosed in "A New NMOS Temperature Stable Voltage Reference" by Blauschild et al. published in the IEEE Journal of Solid State, Vol. SC13, No. 6, Dec. 1978, beginning at page 677. However, such a circuit includes sixteen FETs to achieve its purposes. On the other hand, the subject circuit includes only four FETs functioning as a reference voltage source and amplifier and one FET functioning as a linear pass regulator transistor.
Presently known linear voltage regulator circuits using insulated gate field effect transistors (IGFET) are difficult to produce with a narrowly predictable output voltage in MOS LSI devices because of circuit sensitivity to transistor threshold voltage (Vth), process variations relating to oxide thickness, substrate resistivity and other yield affecting factors. The invention circuit provides a very predictable output voltage and is particularly compatible with manufacturing techniques in MOS processes for structuring n-channel, p-channel, metal gate or silicon gate devices using single or double polysilicon layers.